1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a master slice semiconductor integrated circuit which uses a plurality of power source voltages.
2. Description of the Prior Art
FIG. 7 is a plan view showing the chip structure of a conventional master slice semiconductor integrated circuit. FIG. 8 is a plan view enlarging a region X of FIG. 7 to show the structure of a cell and a region around the same. To dispose cells which form input/output circuits which attain input to and output from an inner region 5, a first semiconductor region 3 of a first conductivity type and a second semiconductor region 4 of a second conductivity type are formed on a peripheral portion of the inner region 5. Input/output pads 1 are connected to the input/output circuits through metal wires 2. Power source wires 7 and 8 are disposed above the first and the second semiconductor regions 3 and 4, respectively. For simplicity of illustration, FIG. 8 does not show in detail how the metal wires 2 are connected to the first and the second semiconductor regions 3 and 4.
FIG. 9 is a cross sectional view of one of the cells and FIG. 10 is a perspective cross sectional view showing a portion of the array of the cells. The first and the second semiconductor regions 3 and 4 are formed in the same substrate 15 as a well. In the first and the second semiconductor regions 3 and 4, a MOS transistor of the second conductivity type and a MOS transistor of the first conductivity type are respectively formed. The MOS transistors of the two different types form an invertor circuit in the cell so that the cell functions as an input/output circuit.
The MOS transistor formed in the first semiconductor region 3 comprises a gate electrode 10, source and drain diffusion regions 12a of the second conductivity type, and a diffusion region 12b of the first conductivity type to which a back gate voltage is applied. Similarly, the MOS transistor formed in the second semiconductor region 4 comprises a gate electrode 9, source and drain diffusion regions 11a of the first conductivity type, and a diffusion region 11b of the second conductivity type for receiving a back gate voltage. FIGS. 7 and 8 omit these for simplicity of illustration.
Fabrication of a master slice semiconductor integrated circuit, that is, a large scale integrated circuit, involves master process for forming a transistor, and slicing process which includes formation of contacts, wiring layers and via holes. In other words, after obtaining a master structure, the cells as that shown in FIG. 8 are arranged on the master structure in accordance with predetermined data during the slicing process so that the LSI as that shown in FIG. 7 is eventually manufactured.
Having such a construction, the conventional master slice LSI receives a potential V1 to the second semiconductor region 4 through the diffusion region 11b (which receives the back gate voltage) of the second conductivity type and receives a potential GND (i.e., a ground potential) to the first semiconductor region 3 through the diffusion region 12b (which receives the back gate voltage) of the first conductivity type.
On the other hand, the cells which arc distinctive from each other are formed in the same well. Hence, when different power source potentials are given to different cells, the potentials would short circuit since only one potential is allowed to each one of the first and the second semiconductor regions 3 and 4.